diff options
Diffstat (limited to 'src/main/scala/firrtl/backends')
| -rw-r--r-- | src/main/scala/firrtl/backends/experimental/smt/StutteringClockTransform.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/backends/experimental/smt/StutteringClockTransform.scala b/src/main/scala/firrtl/backends/experimental/smt/StutteringClockTransform.scala index 5db39ac9..534db217 100644 --- a/src/main/scala/firrtl/backends/experimental/smt/StutteringClockTransform.scala +++ b/src/main/scala/firrtl/backends/experimental/smt/StutteringClockTransform.scala @@ -11,6 +11,7 @@ import firrtl.passes.PassException import firrtl.stage.Forms import firrtl.stage.TransformManager.TransformDependency import firrtl.transforms.PropagatePresetAnnotations +import firrtl.renamemap.MutableRenameMap import scala.collection.mutable @@ -94,7 +95,7 @@ class StutteringClockTransform extends Transform with DependencyAPIMigration { // rename clocks to clock enable signals val mRef = CircuitTarget(state.circuit.main).module(main.name) - val renameMap = RenameMap() + val renameMap = MutableRenameMap() scan.clockToEnable.foreach { case (clk, en) => renameMap.record(mRef.ref(clk), mRef.ref(en.name)) |