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-rw-r--r--src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
index 30d2e891..2634a8e1 100644
--- a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
+++ b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
@@ -511,7 +511,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
}
private val emissionAnnos = annotations.collect {
- case m: SingleTargetAnnotation[ReferenceTarget] @unchecked with EmissionOption => m
+ case m: SingleTargetAnnotation[ReferenceTarget] @unchecked & EmissionOption => m
}
annotations.foreach {