1 files changed, 16 insertions, 13 deletions

diff --git a/src/main/scala/firrtl/backends/experimental/smt/SMTEmitter.scala b/src/main/scala/firrtl/backends/experimental/smt/SMTEmitter.scala
index 322b8961..1c7ea42f 100644
--- a/src/main/scala/firrtl/backends/experimental/smt/SMTEmitter.scala
+++ b/src/main/scala/firrtl/backends/experimental/smt/SMTEmitter.scala
@@ -11,8 +11,10 @@ import firrtl.options.Viewer.view
 import firrtl.options.{CustomFileEmission, Dependency}
 import firrtl.stage.FirrtlOptions
 
-
-private[firrtl] abstract class SMTEmitter private[firrtl] () extends Transform with Emitter with DependencyAPIMigration {
+private[firrtl] abstract class SMTEmitter private[firrtl] ()
+    extends Transform
+    with Emitter
+    with DependencyAPIMigration {
   override def prerequisites: Seq[Dependency[Transform]] = Seq(Dependency(FirrtlToTransitionSystem))
   override def invalidates(a: Transform): Boolean = false
 
@@ -30,16 +32,16 @@ private[firrtl] abstract class SMTEmitter private[firrtl] () extends Transform w
 
   override protected def execute(state: CircuitState): CircuitState = {
     val emitCircuit = state.annotations.exists {
-      case EmitCircuitAnnotation(a) if this.getClass == a => true
+      case EmitCircuitAnnotation(a) if this.getClass == a    => true
       case EmitAllModulesAnnotation(a) if this.getClass == a => error("EmitAllModulesAnnotation not supported!")
-      case _ => false
+      case _                                                 => false
     }
 
-    if(!emitCircuit) { return state }
+    if (!emitCircuit) { return state }
 
     logger.warn(BleedingEdgeWarning)
 
-    val sys = state.annotations.collectFirst{ case TransitionSystemAnnotation(sys) => sys }.getOrElse {
+    val sys = state.annotations.collectFirst { case TransitionSystemAnnotation(sys) => sys }.getOrElse {
       error("Could not find the transition system!")
     }
     state.copy(annotations = state.annotations :+ serialize(sys))
@@ -52,11 +54,12 @@ private[firrtl] abstract class SMTEmitter private[firrtl] () extends Transform w
 }
 
 case class EmittedSMTModelAnnotation(name: String, src: String, outputSuffix: String)
-  extends NoTargetAnnotation with CustomFileEmission {
+    extends NoTargetAnnotation
+    with CustomFileEmission {
   override protected def baseFileName(annotations: AnnotationSeq): String =
     view[FirrtlOptions](annotations).outputFileName.getOrElse(name)
   override protected def suffix: Option[String] = Some(outputSuffix)
-  override def getBytes: Iterable[Byte] = src.getBytes
+  override def getBytes:         Iterable[Byte] = src.getBytes
 }
 
 private[firrtl] class Btor2Emitter extends SMTEmitter {
@@ -72,14 +75,14 @@ private[firrtl] class SMTLibEmitter extends SMTEmitter {
   override protected def serialize(sys: TransitionSystem): Annotation = {
     val hasMemory = sys.states.exists(_.sym.isInstanceOf[ArrayExpr])
     val logic = SMTLibSerializer.setLogic(hasMemory) + "\n"
-    val header = if(hasMemory) {
+    val header = if (hasMemory) {
       "; We have to disable the logic for z3 to accept the non-standard \"as const\"\n" +
-      "; see https://github.com/Z3Prover/z3/issues/1803\n" +
-      "; for CVC4 you probably want to include the logic\n" +
-      ";" + logic
+        "; see https://github.com/Z3Prover/z3/issues/1803\n" +
+        "; for CVC4 you probably want to include the logic\n" +
+        ";" + logic
     } else { logic }
     val smt = generatedHeader("SMT-LIBv2", sys.name) + header +
       SMTTransitionSystemEncoder.encode(sys).map(SMTLibSerializer.serialize).mkString("\n") + "\n"
     EmittedSMTModelAnnotation(sys.name, smt, outputSuffix)
   }
-}
\ No newline at end of file
+}