1 files changed, 19 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/annotations/PresetAnnotations.scala b/src/main/scala/firrtl/annotations/PresetAnnotations.scala
index 32f24f13..449679cc 100644
--- a/src/main/scala/firrtl/annotations/PresetAnnotations.scala
+++ b/src/main/scala/firrtl/annotations/PresetAnnotations.scala
@@ -17,15 +17,31 @@ case class PresetAnnotation(target: ReferenceTarget)
 
 /**
   * Transform the targeted asynchronously-reset Reg into a bitstream preset Reg
-  * Used internally to annotate all registers associated to an AsyncReset tree
+  * Thus you can use this annotation in order to initialize a register
+  * at the beginning of simulation or through the FPGA bit-stream to its `init` value.
+  *
+  * The register must fulfil the following requirements:
+  * - the reset signal is `UInt(0)`
+  * - the `init` value is a Literal
   *
   * @param target ReferenceTarget to a Reg
   */
-private[firrtl] case class PresetRegAnnotation(
+case class PresetRegAnnotation(
   target: ReferenceTarget)
     extends SingleTargetAnnotation[ReferenceTarget]
-    with RegisterEmissionOption {
+    with RegisterEmissionOption
+    with firrtl.transforms.DontTouchAllTargets {
   def duplicate(n: ReferenceTarget) = this.copy(target = n)
   override def useInitAsPreset = true
   override def disableRandomization = true
 }
+
+object PresetRegAnnotation {
+
+  /** Extracts the names of every preset reg in the design by module. */
+  def collect(annotations: AnnotationSeq, main: String): Map[String, Set[String]] =
+    annotations.collect {
+      case a: PresetRegAnnotation if a.target.circuit == main =>
+        a.target.module -> a.target.ref
+    }.groupBy(_._1).map { case (k, v) => k -> v.map(_._2).toSet }
+}