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Diffstat (limited to 'src/main/scala/firrtl/analyses/ConnectionGraph.scala')
| -rw-r--r-- | src/main/scala/firrtl/analyses/ConnectionGraph.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/analyses/ConnectionGraph.scala b/src/main/scala/firrtl/analyses/ConnectionGraph.scala index e5e3bde2..32bb1564 100644 --- a/src/main/scala/firrtl/analyses/ConnectionGraph.scala +++ b/src/main/scala/firrtl/analyses/ConnectionGraph.scala @@ -416,6 +416,7 @@ object ConnectionGraph { case firrtl.ir.Field(name, Default, tpe) => Utils.create_exps(Reference(name, tpe, PortKind, SourceFlow)) // Module input case firrtl.ir.Field(name, Flip, tpe) => Utils.create_exps(Reference(name, tpe, PortKind, SinkFlow)) + case x => Utils.error(s"Unexpected flip: ${x.flip}") } assert(instPorts.size == modulePorts.size) val o = m.circuitTarget.module(ofModule) |