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-rw-r--r--src/main/scala/firrtl/StringLit.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/StringLit.scala b/src/main/scala/firrtl/StringLit.scala
index 501e9686..b34fc498 100644
--- a/src/main/scala/firrtl/StringLit.scala
+++ b/src/main/scala/firrtl/StringLit.scala
@@ -111,11 +111,11 @@ object VerilogStringLitHandler extends StringLitHandler {
def format(in: Array[Byte], out: Array[Byte], percent: Boolean): Array[Byte] = {
if (in.isEmpty) out
else {
- if (percent && in.head == 'x') format(in.tail, out :+ 'h'.toByte, false)
+ if (percent && in.head == 'x') format(in.tail, out :+ 'h'.toByte, percent = false)
else format(in.tail, out :+ in.head, in.head == '%' && !percent)
}
}
- StringLit(format(lit.array, Array(), false))
+ StringLit(format(lit.array, Array(), percent = false))
}
}