diff options
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 33553179..f42d11ba 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -146,7 +146,7 @@ class EmitVerilogFromLowFirrtl(val writer: Writer) extends Transform with Simple passes.ConstProp, passes.Legalize, passes.VerilogWrap, - passes.VerilogMemDelays, + passes.memlib.VerilogMemDelays, passes.ConstProp, passes.SplitExpressions, passes.CommonSubexpressionElimination, @@ -191,7 +191,7 @@ class LowFirrtlCompiler extends Compiler { new passes.InlineInstances(TransID(0)), new ResolveAndCheck, new HighFirrtlToMiddleFirrtl, - new passes.InferReadWrite(TransID(-1)), + new passes.memlib.InferReadWrite(TransID(-1)), new passes.memlib.ReplSeqMem(TransID(-2)), new MiddleFirrtlToLowFirrtl, new EmitFirrtl(writer) @@ -205,7 +205,7 @@ class VerilogCompiler extends Compiler { new IRToWorkingIR, new ResolveAndCheck, new HighFirrtlToMiddleFirrtl, - new passes.InferReadWrite(TransID(-1)), + new passes.memlib.InferReadWrite(TransID(-1)), new passes.memlib.ReplSeqMem(TransID(-2)), new MiddleFirrtlToLowFirrtl, new passes.InlineInstances(TransID(0)), |