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Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index b9042781..84f237a3 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -6,7 +6,6 @@ sealed abstract class CoreTransform extends SeqTransform /** This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting * circuit has only IR nodes, not WIR. - * TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL */ class ChirrtlToHighFirrtl extends CoreTransform { def inputForm = ChirrtlForm @@ -75,7 +74,6 @@ class HighFirrtlToMiddleFirrtl extends CoreTransform { /** Expands all aggregate types into many ground-typed components. Must * accept a well-formed graph of only middle Firrtl features. * Operates on working IR nodes. - * TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL */ class MiddleFirrtlToLowFirrtl extends CoreTransform { def inputForm = MidForm |