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-rw-r--r--src/main/scala/firrtl/LoweringCompilers.scala2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 14d222f6..19e7d8c6 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -3,7 +3,6 @@
package firrtl
import firrtl.transforms.IdentityTransform
-import firrtl.options.StageUtils
import firrtl.stage.{Forms, TransformManager}
@deprecated("Use a TransformManager or some other Stage/Phase class. Will be removed in 1.4.", "FIRRTL 1.2")
@@ -174,5 +173,4 @@ class MinimumVerilogCompiler extends Compiler {
)
class SystemVerilogCompiler extends VerilogCompiler {
override val emitter = new SystemVerilogEmitter
- StageUtils.dramaticWarning("SystemVerilog Compiler behaves the same as the Verilog Compiler!")
}