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Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index cd77fa3e..c7b7f5dd 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -145,6 +145,8 @@ class EmitVerilogFromLowFirrtl(val writer: Writer) extends Transform with Simple passes.ConstProp, passes.Legalize, passes.VerilogWrap, + passes.VerilogMemDelays, + passes.ConstProp, passes.SplitExpressions, passes.CommonSubexpressionElimination, passes.DeadCodeElimination, |