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Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 3db83406..33cb70db 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -30,6 +30,7 @@ package firrtl import com.typesafe.scalalogging.LazyLogging import java.io.Writer import firrtl.passes.Pass +import firrtl.ir.Circuit // =========================================== // Utility Traits @@ -67,7 +68,7 @@ class Chisel3ToHighFirrtl () extends Transform with SimpleRun { run(circuit, passSeq) } -// Converts from the bare intermediate representation (IR.scala) +// Converts from the bare intermediate representation (ir.scala) // to a working representation (WIR.scala) class IRToWorkingIR () extends Transform with SimpleRun { val passSeq = Seq(passes.ToWorkingIR) |