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Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index c7b7f5dd..eb44b4c2 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -150,7 +150,8 @@ class EmitVerilogFromLowFirrtl(val writer: Writer) extends Transform with Simple passes.SplitExpressions, passes.CommonSubexpressionElimination, passes.DeadCodeElimination, - passes.VerilogRename) + passes.VerilogRename, + passes.VerilogPrep) def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = { val result = run(circuit, passSeq) (new VerilogEmitter).run(result.circuit, writer) |