1 files changed, 5 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index e27cafb7..e0bde64f 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -123,7 +123,7 @@ class NoneCompiler extends Compiler {
 )
 class HighFirrtlCompiler extends Compiler {
   val emitter = new HighFirrtlEmitter
-  def transforms: Seq[Transform] = Forms.HighForm.map(_.getObject)
+  def transforms: Seq[Transform] = Forms.HighForm.map(_.getObject())
 }
 
 /** Emits middle Firrtl input circuit */
@@ -133,7 +133,7 @@ class HighFirrtlCompiler extends Compiler {
 )
 class MiddleFirrtlCompiler extends Compiler {
   val emitter = new MiddleFirrtlEmitter
-  def transforms: Seq[Transform] = Forms.MidForm.map(_.getObject)
+  def transforms: Seq[Transform] = Forms.MidForm.map(_.getObject())
 }
 
 /** Emits lowered input circuit */
@@ -143,7 +143,7 @@ class MiddleFirrtlCompiler extends Compiler {
 )
 class LowFirrtlCompiler extends Compiler {
   val emitter = new LowFirrtlEmitter
-  def transforms: Seq[Transform] = Forms.LowForm.map(_.getObject)
+  def transforms: Seq[Transform] = Forms.LowForm.map(_.getObject())
 }
 
 /** Emits Verilog */
@@ -153,7 +153,7 @@ class LowFirrtlCompiler extends Compiler {
 )
 class VerilogCompiler extends Compiler {
   val emitter = new VerilogEmitter
-  def transforms: Seq[Transform] = Forms.LowFormOptimized.map(_.getObject)
+  def transforms: Seq[Transform] = Forms.LowFormOptimized.map(_.getObject())
 }
 
 /** Emits Verilog without optimizations */
@@ -163,7 +163,7 @@ class VerilogCompiler extends Compiler {
 )
 class MinimumVerilogCompiler extends Compiler {
   val emitter = new MinimumVerilogEmitter
-  def transforms: Seq[Transform] = Forms.LowFormMinimumOptimized.map(_.getObject)
+  def transforms: Seq[Transform] = Forms.LowFormMinimumOptimized.map(_.getObject())
 }
 
 /** Currently just an alias for the [[VerilogCompiler]] */