diff options
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 186 |
1 files changed, 64 insertions, 122 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 446df6d0..986ebd9f 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -27,59 +27,38 @@ MODIFICATIONS. package firrtl -import java.io.Writer -import firrtl.passes.Pass -import firrtl.ir.Circuit -import Annotations._ -import logger.LazyLogging +sealed abstract class CoreTransform extends PassBasedTransform -// =========================================== -// Utility Traits -// ------------------------------------------- -// Valid if all passes in transformation: -// 1) Don't produce annotations -// 2) Don't consume annotations -// 3) No component or module names are renamed -trait SimpleRun extends LazyLogging { - def run (circuit: Circuit, passes: Seq[Pass]): TransformResult = { - val result = (passes foldLeft circuit){ (c: Circuit, pass: Pass) => - val name = pass.name - val x = Utils.time(name)(pass.run(c)) - logger.debug(x.serialize) - x - } - TransformResult(result) - } -} - -// =========================================== -// Lowering Transforms -// ------------------------------------------- -// This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting -// circuit has only IR nodes, not WIR. -// TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL -class Chisel3ToHighFirrtl extends Transform with SimpleRun { - val passSeq = Seq( +/** This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting + * circuit has only IR nodes, not WIR. + * TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL + */ +class ChirrtlToHighFirrtl extends CoreTransform { + def inputForm = ChirrtlForm + def outputForm = HighForm + def passSeq = Seq( passes.CheckChirrtl, passes.CInferTypes, passes.CInferMDir, passes.RemoveCHIRRTL) - def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = - run(circuit, passSeq) } -// Converts from the bare intermediate representation (ir.scala) -// to a working representation (WIR.scala) -class IRToWorkingIR extends Transform with SimpleRun { - val passSeq = Seq(passes.ToWorkingIR) - def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = - run(circuit, passSeq) +/** Converts from the bare intermediate representation (ir.scala) + * to a working representation (WIR.scala) + */ +class IRToWorkingIR extends CoreTransform { + def inputForm = HighForm + def outputForm = HighForm + def passSeq = Seq(passes.ToWorkingIR) } -// Resolves types, kinds, and genders, and checks the circuit legality. -// Operates on working IR nodes and high Firrtl. -class ResolveAndCheck extends Transform with SimpleRun { - val passSeq = Seq( +/** Resolves types, kinds, and genders, and checks the circuit legality. + * Operates on working IR nodes and high Firrtl. + */ +class ResolveAndCheck extends CoreTransform { + def inputForm = HighForm + def outputForm = HighForm + def passSeq = Seq( passes.CheckHighForm, passes.ResolveKinds, passes.InferTypes, @@ -91,16 +70,17 @@ class ResolveAndCheck extends Transform with SimpleRun { passes.CheckGenders, passes.InferWidths, passes.CheckWidths) - def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = - run(circuit, passSeq) } -// Expands aggregate connects, removes dynamic accesses, and when -// statements. Checks for uninitialized values. Must accept a -// well-formed graph. -// Operates on working IR nodes. -class HighFirrtlToMiddleFirrtl extends Transform with SimpleRun { - val passSeq = Seq( +/** Expands aggregate connects, removes dynamic accesses, and when + * statements. Checks for uninitialized values. Must accept a + * well-formed graph. + * Operates on working IR nodes. + */ +class HighFirrtlToMiddleFirrtl extends CoreTransform { + def inputForm = HighForm + def outputForm = MidForm + def passSeq = Seq( passes.PullMuxes, passes.ReplaceAccesses, passes.ExpandConnects, @@ -112,16 +92,17 @@ class HighFirrtlToMiddleFirrtl extends Transform with SimpleRun { passes.ResolveGenders, passes.InferWidths, passes.CheckWidths) - def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = - run(circuit, passSeq) } -// Expands all aggregate types into many ground-typed components. Must -// accept a well-formed graph of only middle Firrtl features. -// Operates on working IR nodes. -// TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL -class MiddleFirrtlToLowFirrtl extends Transform with SimpleRun { - val passSeq = Seq( +/** Expands all aggregate types into many ground-typed components. Must + * accept a well-formed graph of only middle Firrtl features. + * Operates on working IR nodes. + * TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL + */ +class MiddleFirrtlToLowFirrtl extends CoreTransform { + def inputForm = MidForm + def outputForm = LowForm + def passSeq = Seq( passes.LowerTypes, passes.ResolveKinds, passes.InferTypes, @@ -129,87 +110,48 @@ class MiddleFirrtlToLowFirrtl extends Transform with SimpleRun { passes.InferWidths, passes.ConvertFixedToSInt, passes.Legalize) - def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = - run(circuit, passSeq) } -// Emits Verilog. -// First optimizes for verilog width semantics with custom Primops, -// then splits complex expressions into temporary nodes. Finally, -// renames names that conflict with Verilog keywords. -// Operates on working IR nodes. -// TODO(izraelevitz): Create RenameMap from VerilogRename -class EmitVerilogFromLowFirrtl(val writer: Writer) extends Transform with SimpleRun { - val passSeq = Seq( +/** Runs a series of optimization passes on LowFirrtl + * @note This is currently required for correct Verilog emission + * TODO Fix the above note + */ +class LowFirrtlOptimization extends CoreTransform { + def inputForm = LowForm + def outputForm = LowForm + def passSeq = Seq( passes.RemoveValidIf, passes.ConstProp, passes.PadWidths, passes.ConstProp, passes.Legalize, - passes.VerilogWrap, - passes.memlib.VerilogMemDelays, + passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter passes.ConstProp, passes.SplitExpressions, passes.CommonSubexpressionElimination, - passes.DeadCodeElimination, - passes.VerilogRename, - passes.VerilogPrep) - def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = { - val result = run(circuit, passSeq) - (new VerilogEmitter).run(result.circuit, writer) - result - } + passes.DeadCodeElimination) } -// Emits Firrtl. -// Operates on WIR/IR nodes. -class EmitFirrtl(val writer: Writer) extends Transform { - def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = { - FIRRTLEmitter.run(circuit, writer) - TransformResult(circuit) - } -} +import CompilerUtils.getLoweringTransforms -// =========================================== -// Lowering Compilers -// ------------------------------------------- -// Emits input circuit -// Will replace Chirrtl constructs with Firrtl +/** Emits input circuit + * Will replace Chirrtl constructs with Firrtl + */ class HighFirrtlCompiler extends Compiler { - def transforms(writer: Writer): Seq[Transform] = Seq( - new Chisel3ToHighFirrtl, - new IRToWorkingIR, - new EmitFirrtl(writer) - ) + def emitter = new FirrtlEmitter + def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, HighForm) } -// Emits lowered input circuit +/** Emits lowered input circuit */ class LowFirrtlCompiler extends Compiler { - def transforms(writer: Writer): Seq[Transform] = Seq( - new Chisel3ToHighFirrtl, - new IRToWorkingIR, - new passes.InlineInstances(TransID(0)), - new ResolveAndCheck, - new HighFirrtlToMiddleFirrtl, - new passes.memlib.InferReadWrite(TransID(-1)), - new passes.memlib.ReplSeqMem(TransID(-2)), - new MiddleFirrtlToLowFirrtl, - new EmitFirrtl(writer) - ) + def emitter = new FirrtlEmitter + def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, LowForm) } -// Emits Verilog +/** Emits Verilog */ class VerilogCompiler extends Compiler { - def transforms(writer: Writer): Seq[Transform] = Seq( - new Chisel3ToHighFirrtl, - new IRToWorkingIR, - new ResolveAndCheck, - new HighFirrtlToMiddleFirrtl, - new passes.memlib.InferReadWrite(TransID(-1)), - new passes.memlib.ReplSeqMem(TransID(-2)), - new MiddleFirrtlToLowFirrtl, - new passes.InlineInstances(TransID(0)), - new EmitVerilogFromLowFirrtl(writer) - ) + def emitter = new VerilogEmitter + def transforms: Seq[Transform] = + getLoweringTransforms(ChirrtlForm, LowForm) :+ (new LowFirrtlOptimization) } |