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-rw-r--r--src/main/scala/firrtl/LoweringCompilers.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 307ef9d1..53491922 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -192,7 +192,7 @@ class LowFirrtlCompiler extends Compiler {
new ResolveAndCheck,
new HighFirrtlToMiddleFirrtl,
new passes.InferReadWrite(TransID(-1)),
- new passes.ReplSeqMem(TransID(-2)),
+ new passes.memlib.ReplSeqMem(TransID(-2)),
new MiddleFirrtlToLowFirrtl,
new EmitFirrtl(writer)
)
@@ -206,7 +206,7 @@ class VerilogCompiler extends Compiler {
new ResolveAndCheck,
new HighFirrtlToMiddleFirrtl,
new passes.InferReadWrite(TransID(-1)),
- new passes.ReplSeqMem(TransID(-2)),
+ new passes.memlib.ReplSeqMem(TransID(-2)),
new MiddleFirrtlToLowFirrtl,
new passes.InlineInstances(TransID(0)),
new EmitVerilogFromLowFirrtl(writer)