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Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 44d3a757..5201942a 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -110,6 +110,7 @@ class LowFirrtlOptimization extends CoreTransform { import CompilerUtils.getLoweringTransforms +import firrtl.transforms.BlackBoxSourceHelper /** Emits input circuit * Will replace Chirrtl constructs with Firrtl @@ -135,5 +136,5 @@ class LowFirrtlCompiler extends Compiler { class VerilogCompiler extends Compiler { def emitter = new VerilogEmitter def transforms: Seq[Transform] = - getLoweringTransforms(ChirrtlForm, LowForm) :+ (new LowFirrtlOptimization) + getLoweringTransforms(ChirrtlForm, LowForm) ++ Seq(new LowFirrtlOptimization, new BlackBoxSourceHelper) } |