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-rw-r--r--src/main/scala/firrtl/LoweringCompilers.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 66ae1673..8dd9b180 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -98,12 +98,12 @@ class LowFirrtlOptimization extends CoreTransform {
def outputForm = LowForm
def transforms = Seq(
passes.RemoveValidIf,
- passes.ConstProp,
+ new firrtl.transforms.ConstantPropagation,
passes.PadWidths,
- passes.ConstProp,
+ new firrtl.transforms.ConstantPropagation,
passes.Legalize,
passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter
- passes.ConstProp,
+ new firrtl.transforms.ConstantPropagation,
passes.SplitExpressions,
passes.CommonSubexpressionElimination,
new firrtl.transforms.DeadCodeElimination)