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-rw-r--r--src/main/scala/firrtl/LoweringCompilers.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index eab928c2..7499d6d1 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -166,9 +166,9 @@ class VerilogCompiler extends Compiler {
/** Emits Verilog without optimizations */
class MinimumVerilogCompiler extends Compiler {
- def emitter = new VerilogEmitter
+ def emitter = new MinimumVerilogEmitter
def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, LowForm) ++
- Seq(new MinimumLowFirrtlOptimization, new BlackBoxSourceHelper)
+ Seq(new MinimumLowFirrtlOptimization)
}
/** Currently just an alias for the [[VerilogCompiler]] */