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Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index ba686f08..dce6bac9 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -149,7 +149,7 @@ class LowFirrtlCompiler extends Compiler { class VerilogCompiler extends Compiler { def emitter = new VerilogEmitter def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, LowForm) ++ - Seq(new LowFirrtlOptimization, new BlackBoxSourceHelper) + Seq(new LowFirrtlOptimization) } /** Emits Verilog without optimizations */ |