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Diffstat (limited to 'src/main/scala/firrtl/IR.scala')
| -rw-r--r-- | src/main/scala/firrtl/IR.scala | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala index c762b198..7721a563 100644 --- a/src/main/scala/firrtl/IR.scala +++ b/src/main/scala/firrtl/IR.scala @@ -167,13 +167,22 @@ case object OUTPUT extends Direction case class Port(info: Info, name: String, direction: Direction, tpe: Type) extends AST with IsDeclaration -trait Module extends AST with IsDeclaration { +/** Base class for modules */ +abstract class DefModule extends AST with IsDeclaration { val info : Info val name : String val ports : Seq[Port] } -case class InModule(info: Info, name: String, ports: Seq[Port], body: Stmt) extends Module -case class ExModule(info: Info, name: String, ports: Seq[Port]) extends Module - -case class Circuit(info: Info, modules: Seq[Module], main: String) extends AST with HasInfo +/** Internal Module + * + * An instantiable hardware block + */ +case class Module(info: Info, name: String, ports: Seq[Port], body: Stmt) extends DefModule +/** External Module + * + * Generally used for Verilog black boxes + */ +case class ExtModule(info: Info, name: String, ports: Seq[Port]) extends DefModule + +case class Circuit(info: Info, modules: Seq[DefModule], main: String) extends AST with HasInfo |