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Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 42137605..7ee652af 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -978,6 +978,7 @@ class VerilogEmitter extends SeqTransform with Emitter { /** Preamble for every emitted Verilog file */ def transforms = Seq( new BlackBoxSourceHelper, + new FixAddingNegativeLiterals, new ReplaceTruncatingArithmetic, new InlineNotsTransform, new InlineBitExtractionsTransform, // here after InlineNots to clean up not(not(...)) rename |