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Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index f96c0419..435bc484 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -426,7 +426,7 @@ class VerilogEmitter extends Emitter { } } - def build_ports: Unit = m.ports.zipWithIndex foreach {case (p, i) => + def build_ports(): Unit = m.ports.zipWithIndex foreach {case (p, i) => p.direction match { case Input => portdefs += Seq(p.direction, " ", p.tpe, " ", p.name) @@ -602,7 +602,7 @@ class VerilogEmitter extends Emitter { case s => s } - def emit_streams { + def emit_streams() { emit(Seq("module ", m.name, "(")) for ((x, i) <- portdefs.zipWithIndex) { if (i != portdefs.size - 1) |