diff options
Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 92cb7a54..902dfecd 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -163,9 +163,9 @@ class VerilogEmitter extends Emitter { case (t: UIntType) => e case (t: SIntType) => Seq("$signed(",e,")") } - def a0: Expression = doprim.args(0) + def a0: Expression = doprim.args.head def a1: Expression = doprim.args(1) - def c0: Int = doprim.consts(0).toInt + def c0: Int = doprim.consts.head.toInt def c1: Int = doprim.consts(1).toInt def checkArgumentLegality(e: Expression) = e match { |