diff options
Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index b1c318fa..1153b1e6 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -248,8 +248,11 @@ class VerilogEmitter extends Transform with PassBased with Emitter { case UIntLiteral(value, IntWidth(width)) => w write s"$width'h${value.toString(16)}" case SIntLiteral(value, IntWidth(width)) => - val unsignedValue = value + (if (value < 0) BigInt(1) << width.toInt else 0) - w write s"$width'sh${unsignedValue.toString(16)}" + val stringLiteral = value.toString(16) + w write (stringLiteral.head match { + case '-' => s"-$width'sh${stringLiteral.tail}" + case _ => s"$width'sh${stringLiteral}" + }) } def op_stream(doprim: DoPrim): Seq[Any] = { |