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Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index e3a146e2..5a4420c6 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -89,6 +89,7 @@ class VerilogEmitter extends Emitter { case StringParam(name, value) => val strx = "\"" + VerilogStringLitHandler.escape(value) + "\"" s".${name}($strx)" + case RawStringParam(name, value) => s".$name($value)" } def emit(x: Any)(implicit w: Writer) { emit(x, 0) } def emit(x: Any, top: Int)(implicit w: Writer) { |