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-rw-r--r--src/main/scala/firrtl/Emitter.scala7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 1044f047..b5474769 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -265,7 +265,12 @@ class VerilogEmitter extends SeqTransform with Emitter {
case (i: BigInt) => w write i.toString
case (i: Info) => i match {
case NoInfo => // Do nothing
- case ix => w.write(s" //$ix")
+ case f: FileInfo =>
+ val escaped = FileInfo.escapedToVerilog(f.escaped)
+ w.write(s" // @[$escaped]")
+ case m: MultiInfo =>
+ val escaped = FileInfo.escapedToVerilog(m.flatten.map(_.escaped).mkString(" "))
+ w.write(s" // @[$escaped]")
}
case (s: Seq[Any]) =>
s foreach (emit(_, top + 1))