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-rw-r--r--src/main/scala/firrtl/Emitter.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 1455b912..7af2017c 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -56,7 +56,7 @@ object FIRRTLEmitter extends Emitter {
case class VIndent()
case object VRandom extends Expression {
- def tpe = UIntType(UnknownWidth())
+ def tpe = UIntType(UnknownWidth)
}
class VerilogEmitter extends Emitter {
val tab = " "