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Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 59aee8c4..ceccccbc 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -77,6 +77,7 @@ class VerilogEmitter extends Emitter { (tpe(e)) match { case (t:UIntType) => e case (t:SIntType) => Seq("$signed(",e,")") + case (t:ClockType) => e } } (x) match { |