1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index b099dd55..e9c90fd6 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -37,6 +37,7 @@ import scala.io.Source
 
 import Utils._
 import firrtl.Serialize._
+import firrtl.Mappers._
 import firrtl.passes._
 import WrappedExpression._
 // Datastructures
@@ -279,7 +280,7 @@ object VerilogEmitter extends Emitter {
                val e = WRef(s.name,get_type(s),NodeKind(),MALE)
                netlist(e) = s.value
             }
-            case (s) => sMap(build_netlist,s)
+            case (s) => s map (build_netlist)
          }
          s
       }
@@ -529,7 +530,7 @@ object VerilogEmitter extends Emitter {
                   update(wmem_port,datax,clk,AND(AND(enx,maskx),wmode))
                }
             }
-            case (s:Begin) => sMap(build_streams _,s)
+            case (s:Begin) => s map (build_streams)
          }
          s
       }