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Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 0a743321..e28a3d20 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -822,7 +822,7 @@ class VerilogEmitter extends SeqTransform with Emitter { new FlattenRegUpdate, new DeadCodeElimination, passes.VerilogModulusCleanup, - passes.VerilogRename, + new VerilogRename, passes.VerilogPrep, new AddDescriptionNodes) |