diff options
Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index c8657131..1b171d3a 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -89,9 +89,8 @@ class VerilogEmitter extends Emitter { case (e:WSubField) => w.get.write(LowerTypes.loweredName(e)) case (e:WSubAccess) => w.get.write(LowerTypes.loweredName(e.exp) + "[" + LowerTypes.loweredName(e.index) + "]") case (e:WSubIndex) => w.get.write(e.serialize) - case (_:UIntValue|_:SIntValue) => v_print(e) + case (e:Literal) => v_print(e) case VRandom => w.get.write("$random") - } } case (t:Type) => { @@ -126,11 +125,11 @@ class VerilogEmitter extends Emitter { //;------------- PASS ----------------- def v_print (e:Expression) = { e match { - case (e:UIntValue) => { + case (e:UIntLiteral) => { val str = e.value.toString(16) w.get.write(long_BANG(tpe(e)).toString + "'h" + str) } - case (e:SIntValue) => { + case (e:SIntLiteral) => { val str = e.value.toString(16) w.get.write(long_BANG(tpe(e)).toString + "'sh" + str) } @@ -164,8 +163,8 @@ class VerilogEmitter extends Emitter { def c1 () : Int = doprim.consts(1).toInt def checkArgumentLegality(e: Expression) = e match { - case _: UIntValue => - case _: SIntValue => + case _: UIntLiteral => + case _: SIntLiteral => case _: WRef => case _: WSubField => case _ => throw new EmitterException(s"Can't emit ${e.getClass.getName} as PrimOp argument") |