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Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index e40a18a4..a290ced4 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -562,6 +562,7 @@ class VerilogEmitter extends Emitter with PassBased { } def passSeq = Seq( + passes.VerilogModulusCleanup, passes.VerilogWrap, passes.VerilogRename, passes.VerilogPrep) |