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-rw-r--r--src/main/scala/firrtl/Emitter.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 2788173a..b6162692 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -542,10 +542,10 @@ class VerilogEmitter extends SeqTransform with Emitter {
circuitName: String,
emissionOptions: EmissionOptions)(implicit writer: Writer) {
- def this(m: Module, moduleMap: Map[String, DefModule], circuitName: String, emissionOptions: EmissionOptions)(implicit writer: Writer) {
+ def this(m: Module, moduleMap: Map[String, DefModule], circuitName: String, emissionOptions: EmissionOptions)(implicit writer: Writer) = {
this(Seq(), Map.empty, m, moduleMap, circuitName, emissionOptions)(writer)
}
- def this(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer) {
+ def this(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer) = {
this(Seq(), Map.empty, m, moduleMap, "", new EmissionOptions(Seq.empty))(writer)
}