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-rw-r--r--src/main/scala/firrtl/Emitter.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 195f786d..9bb8a466 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -12,7 +12,7 @@ import scala.io.Source
import firrtl.ir._
import firrtl.passes._
-import firrtl.transforms.{DeadCodeElimination, FlattenRegUpdate}
+import firrtl.transforms._
import firrtl.annotations._
import firrtl.Mappers._
import firrtl.PrimOps._
@@ -659,10 +659,10 @@ class VerilogEmitter extends SeqTransform with Emitter {
/** Preamble for every emitted Verilog file */
def transforms = Seq(
+ new ReplaceTruncatingArithmetic,
new FlattenRegUpdate,
new DeadCodeElimination,
passes.VerilogModulusCleanup,
- passes.VerilogWrap,
passes.VerilogRename,
passes.VerilogPrep)