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Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 8b1360ab..e8423dfe 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -260,7 +260,7 @@ class VerilogEmitter extends Emitter { simlist += s s case (s: DefNode) => - val e = WRef(s.name, get_type(s), NodeKind(), MALE) + val e = WRef(s.name, s.value.tpe, NodeKind(), MALE) netlist(e) = s.value s case (s) => s |