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-rw-r--r--src/main/scala/firrtl/Emitter.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 459404c3..dcf1a1ad 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -182,7 +182,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
override def prerequisites = firrtl.stage.Forms.LowFormOptimized
- override def dependents = Seq.empty
+ override def optionalPrerequisiteOf = Seq.empty
val outputSuffix = ".v"
val tab = " "