diff options
Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index f6354ee6..fd9bfdc3 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -392,6 +392,7 @@ class VerilogEmitter extends Emitter { } def build_streams (s:Stmt) : Stmt = { s match { + case (s:Empty) => s case (s:Connect) => s case (s:DefWire) => declare("wire",s.name,s.tpe) |