aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/Emitter.scala
diff options
context:
space:
mode:
Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
-rw-r--r--src/main/scala/firrtl/Emitter.scala10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 67bd1583..8049e33c 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -882,3 +882,13 @@ class VerilogEmitter extends SeqTransform with Emitter {
state.copy(annotations = newAnnos ++ state.annotations)
}
}
+
+class MinimumVerilogEmitter extends VerilogEmitter with Emitter {
+
+
+ override def transforms = super.transforms.filter{
+ case _: DeadCodeElimination => false
+ case _ => true
+ }
+
+}