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Diffstat (limited to 'src/main/scala/firrtl/Compiler.scala')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index f80825d4..06bd512e 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -238,7 +238,7 @@ trait Transform extends TransformLike[CircuitState] with DependencyAPI[Transform private lazy val fullCompilerSet = new mutable.LinkedHashSet[Dependency[Transform]] ++ Forms.VerilogOptimized - override def dependents: Seq[Dependency[Transform]] = { + override def optionalPrerequisiteOf: Seq[Dependency[Transform]] = { val lowEmitters = Dependency[LowFirrtlEmitter] :: Dependency[VerilogEmitter] :: Dependency[MinimumVerilogEmitter] :: Dependency[SystemVerilogEmitter] :: Nil |