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Diffstat (limited to 'src/main/scala/firrtl/Compiler.scala')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index aa3eeace..c0fa78f0 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -91,7 +91,8 @@ object VerilogCompiler extends Compiler { def run(c: Circuit, w: Writer) { val loweredIR = PassUtils.executePasses(c, passes) - VerilogEmitter.run(loweredIR, w) + val verilogEmitter = new VerilogEmitter + verilogEmitter.run(loweredIR, w) } } |