1 files changed, 7 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 8facc27d..34feab99 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -21,19 +21,23 @@ object FIRRTLCompiler extends Compiler {
 object VerilogCompiler extends Compiler {
   // Copied from Stanza implementation
   val passes = Seq(
-    CheckHighForm,          
-    Resolve,
+    //CheckHighForm,          
     ToWorkingIR,            
     ResolveKinds,
     InferTypes,
     ResolveGenders,
+    InferWidths,
     PullMuxes,
     ExpandConnects,
     RemoveAccesses,
     ExpandWhens,
     CheckInitialization,   
     ConstProp,
-    Resolve,
+    ToWorkingIR,            
+    ResolveKinds,
+    InferTypes,
+    ResolveGenders,
+    InferWidths,
     LowerTypes
   )
   def run(c: Circuit, w: Writer)