1 files changed, 9 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 0bb7510f..782d43cb 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -38,9 +38,16 @@ trait Compiler extends LazyLogging {
 }
 
 object FIRRTLCompiler extends Compiler {
+  val passes = Seq(
+    CInferTypes,
+    CInferMDir,
+    RemoveCHIRRTL,
+    ToWorkingIR,
+    CheckHighForm
+  )
   def run(c: Circuit, w: Writer) = {
-    FIRRTLEmitter.run(c, w)
-    w.close
+    val highForm = PassUtils.executePasses(c, passes)
+    FIRRTLEmitter.run(highForm, w)
   }
 }
 
@@ -84,7 +91,6 @@ object VerilogCompiler extends Compiler {
   {
     val loweredIR = PassUtils.executePasses(c, passes)
     VerilogEmitter.run(loweredIR, w)
-    w.close
   }
 
 }