1 files changed, 65 insertions, 64 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 08ff421f..8efd010c 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -33,73 +33,74 @@ import java.io.Writer
 import Utils._
 import firrtl.passes._
 
-trait Compiler extends LazyLogging {
-  def run(c: Circuit, w: Writer)
+
+// ===========================================
+//                 Annotations
+// -------------------------------------------
+case class AnnotationException(message: String) extends Exception(message)
+trait Named { def name: String }
+case class ModuleName(name: String) extends Named
+case class ComponentName(name: String, module: ModuleName) extends Named
+
+// - Associated with an arbitrary serializable annotation
+trait Annotation {
+   def serialize: String
 }
 
-object FIRRTLCompiler extends Compiler {
-  val passes = Seq(
-    CInferTypes,
-    CInferMDir,
-    RemoveCHIRRTL,
-    ToWorkingIR,
-    CheckHighForm
-  )
-  def run(c: Circuit, w: Writer) = {
-    val highForm = PassUtils.executePasses(c, passes)
-    FIRRTLEmitter.run(highForm, w)
-  }
+// - Used to identify which annotation is consumed by which pass
+trait CircuitAnnotationKind
+case object UnknownCAKind extends CircuitAnnotationKind
+
+// - A collection of annotations on a given circuit
+// - Call update to keep annotations synced with circuit after
+//    a transformation modifies module or component names
+trait CircuitAnnotation {
+   def kind: CircuitAnnotationKind
+   def update (renames: RenameMap): CircuitAnnotation
 }
 
-object VerilogCompiler extends Compiler {
-  // Copied from Stanza implementation
-  val passes = Seq(
-    //CheckHighForm,          
-    //FromCHIRRTL,
-    CInferTypes,
-    CInferMDir,
-    RemoveCHIRRTL,
-    ToWorkingIR,            
-    CheckHighForm,
-    ResolveKinds,
-    InferTypes,
-    CheckTypes,
-    Uniquify,
-    ResolveKinds,
-    InferTypes,
-    ResolveGenders,
-    CheckGenders,
-    InferWidths,
-    CheckWidths,
-    PullMuxes,
-    ExpandConnects,
-    RemoveAccesses,
-    ExpandWhens,
-    CheckInitialization,   
-    ResolveKinds,
-    InferTypes,
-    ResolveGenders,
-    InferWidths,
-    Legalize,
-    LowerTypes,
-    ResolveKinds,
-    InferTypes,
-    ResolveGenders,
-    InferWidths,
-    RemoveValidIf,
-    ConstProp,
-    PadWidths,
-    VerilogWrap,
-    SplitExpressions,
-    CommonSubexpressionElimination,
-    DeadCodeElimination,
-    VerilogRename
-  )
-  def run(c: Circuit, w: Writer)
-  {
-    val loweredIR = PassUtils.executePasses(c, passes)
-    val verilogEmitter = new VerilogEmitter
-    verilogEmitter.run(loweredIR, w)
-  }
+// - A class that contains a map from old name to modified names
+// - Generated by transformations that modify names
+trait RenameMap { def map: Map[Named, Seq[Named]] }
+case class BasicRenameMap(map: Map[Named,Seq[Named]]) extends RenameMap
+
+
+// ===========================================
+//                 Transforms
+// -------------------------------------------
+
+case class TransformResult (
+   circuit: Circuit,
+   renames: Option[RenameMap] = None,
+   annotation: Option[CircuitAnnotation] = None)
 
+// - Transforms a circuit
+// - Can consume multiple CircuitAnnotation's
+trait Transform {
+   def execute (circuit: Circuit, annotations: Seq[CircuitAnnotation]): TransformResult
 }
+
+// ===========================================
+//                 Compilers
+// -------------------------------------------
+
+case class CompilerResult (circuit: Circuit, annotations: Seq[CircuitAnnotation])
+
+// - A sequence of transformations
+// - Call compile to executes each transformation in sequence onto
+//    a given circuit.
+trait Compiler extends LazyLogging {
+   def transforms(w: Writer): Seq[Transform]
+   def compile(circuit: Circuit, annotations: Seq[CircuitAnnotation], writer: Writer): CompilerResult = {
+      transforms(writer).foldLeft(CompilerResult(circuit,annotations))((in: CompilerResult, xform: Transform) => {
+         val result = xform.execute(in.circuit,in.annotations)
+         val in_remapped = result.renames match {
+            case Some(renames) => in.annotations.map(_.update(renames))
+            case None => in.annotations
+         }
+         val full_annotations = in_remapped ++ result.annotation
+         CompilerResult(result.circuit,full_annotations)
+      })
+   }
+}
+