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-rw-r--r--src/main/scala/firrtl/Compiler.scala2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 0bb7510f..34776cf3 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -40,7 +40,6 @@ trait Compiler extends LazyLogging {
object FIRRTLCompiler extends Compiler {
def run(c: Circuit, w: Writer) = {
FIRRTLEmitter.run(c, w)
- w.close
}
}
@@ -84,7 +83,6 @@ object VerilogCompiler extends Compiler {
{
val loweredIR = PassUtils.executePasses(c, passes)
VerilogEmitter.run(loweredIR, w)
- w.close
}
}