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Diffstat (limited to 'src/main/scala/firrtl/Compiler.scala')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index 2998232f..78ea644d 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -23,6 +23,9 @@ object VerilogCompiler extends Compiler { val passes = Seq( //CheckHighForm, //FromCHIRRTL, + CInferTypes, + CInferMDir, + RemoveCHIRRTL, ToWorkingIR, ResolveKinds, InferTypes, |