1 files changed, 46 insertions, 4 deletions

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 6e5cadcd..6c3911d6 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -2,9 +2,10 @@
 
 package firrtl
 
-import logger.LazyLogging
+import logger._
 import java.io.Writer
 import annotations._
+import scala.collection.mutable
 
 import firrtl.ir.Circuit
 import passes.Pass
@@ -14,7 +15,47 @@ import Utils.throwInternalError
  * RenameMap maps old names to modified names.  Generated by transformations
  * that modify names
  */
-case class RenameMap(map: Map[Named, Seq[Named]] = Map[Named, Seq[Named]]())
+object RenameMap {
+  def apply(map: Map[Named, Seq[Named]]) = {
+    val rm = new RenameMap
+    rm.addMap(map)
+    rm
+  }
+  def apply() = new RenameMap
+}
+class RenameMap {
+  val renameMap = new mutable.HashMap[Named, Seq[Named]]()
+  private var circuitName: String = ""
+  private var moduleName: String = ""
+  def setModule(s: String) =
+    moduleName = s
+  def setCircuit(s: String) =
+    circuitName = s
+  def rename(from: String, to: String): Unit = rename(from, Seq(to))
+  def rename(from: String, tos: Seq[String]): Unit = {
+    val fromName = ComponentName(from, ModuleName(moduleName, CircuitName(circuitName)))
+    val tosName = tos map { to =>
+      ComponentName(to, ModuleName(moduleName, CircuitName(circuitName)))
+    }
+    rename(fromName, tosName)
+  }
+  def rename(from: Named, to: Named): Unit = rename(from, Seq(to))
+  def rename(from: Named, tos: Seq[Named]): Unit = (from, tos) match {
+    case (x, Seq(y)) if x == y =>
+    case _ =>
+      renameMap(from) = renameMap.getOrElse(from, Seq.empty) ++ tos
+  }
+  def delete(names: Seq[String]): Unit = names.foreach(delete(_))
+  def delete(name: String): Unit =
+    delete(ComponentName(name, ModuleName(moduleName, CircuitName(circuitName))))
+  def delete(name: Named): Unit = 
+    renameMap(name) = Seq.empty
+  def addMap(map: Map[Named, Seq[Named]]) =
+    renameMap ++= map
+  def serialize: String = renameMap.map { case (k, v) =>
+    k.serialize + "=>" + v.map(_.serialize).mkString(", ")
+  }.mkString("\n")
+}
 
 /**
  * Container of all annotations for a Firrtl compiler.
@@ -172,7 +213,6 @@ abstract class Transform extends LazyLogging {
     }
     logger.trace(s"Circuit:\n${result.circuit.serialize}")
     logger.info(s"======== Finished Transform $name ========\n")
-
     CircuitState(result.circuit, result.form, Some(AnnotationMap(remappedAnnotations)), None)
   }
 
@@ -200,7 +240,7 @@ abstract class Transform extends LazyLogging {
     }
 
     // For each annotation, rename all annotations.
-    val renames = renameOpt.getOrElse(RenameMap()).map
+    val renames = renameOpt.getOrElse(RenameMap()).renameMap
     for {
       anno <- newAnnotations.toSeq
       newAnno <- anno.update(renames.getOrElse(anno.target, Seq(anno.target)))
@@ -217,8 +257,10 @@ trait SeqTransformBased {
 /** For transformations that are simply a sequence of transforms */
 abstract class SeqTransform extends Transform with SeqTransformBased {
   def execute(state: CircuitState): CircuitState = {
+    /*
     require(state.form <= inputForm,
       s"[$name]: Input form must be lower or equal to $inputForm. Got ${state.form}")
+    */
     val ret = runTransforms(state)
     CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames)
   }