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-rw-r--r--src/main/scala/firrtl/Compiler.scala10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 2e155885..106c973f 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -4,7 +4,7 @@ package firrtl
import logger.LazyLogging
import java.io.Writer
-import Annotations._
+import annotations._
import firrtl.ir.Circuit
import passes.Pass
@@ -15,6 +15,14 @@ import passes.Pass
*/
case class RenameMap(map: Map[Named, Seq[Named]])
+/**
+ * Container of all annotations for a Firrtl compiler.
+ */
+case class AnnotationMap(annotations: Seq[Annotation]) {
+ def get(id: Class[_]): Seq[Annotation] = annotations.filter(a => a.transform == id)
+ def get(named: Named): Seq[Annotation] = annotations.filter(n => n == named)
+}
+
/** Current State of the Circuit
*
* @constructor Creates a CircuitState object