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Diffstat (limited to 'src/main/scala/firrtl/AddDescriptionNodes.scala')
| -rw-r--r-- | src/main/scala/firrtl/AddDescriptionNodes.scala | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/AddDescriptionNodes.scala b/src/main/scala/firrtl/AddDescriptionNodes.scala index 359ff6e7..1e17f5bd 100644 --- a/src/main/scala/firrtl/AddDescriptionNodes.scala +++ b/src/main/scala/firrtl/AddDescriptionNodes.scala @@ -5,7 +5,7 @@ package firrtl import firrtl.ir._ import firrtl.annotations._ import firrtl.Mappers._ -import firrtl.options.{Dependency, PreservesAll} +import firrtl.options.Dependency /** * A base trait for `Annotation`s that describe a `FirrtlNode`. @@ -122,7 +122,7 @@ private case class DescribedMod(descriptions: Seq[Description], * @note should only be used by VerilogEmitter, described nodes will * break other transforms. */ -class AddDescriptionNodes extends Transform with DependencyAPIMigration with PreservesAll[Transform] { +class AddDescriptionNodes extends Transform with DependencyAPIMigration { override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[firrtl.transforms.BlackBoxSourceHelper], @@ -141,6 +141,8 @@ class AddDescriptionNodes extends Transform with DependencyAPIMigration with Pre override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Transform) = false + def onStmt(compMap: Map[String, Seq[Description]])(stmt: Statement): Statement = { val s = stmt.map(onStmt(compMap)) val sname = s match { |