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-rw-r--r--src/main/scala/firrtl/AddDescriptionNodes.scala7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/AddDescriptionNodes.scala b/src/main/scala/firrtl/AddDescriptionNodes.scala
index 1ed3259f..2cd8b9f7 100644
--- a/src/main/scala/firrtl/AddDescriptionNodes.scala
+++ b/src/main/scala/firrtl/AddDescriptionNodes.scala
@@ -60,10 +60,9 @@ private case class DescribedMod(description: Description,
def foreachInfo(f: Info => Unit): Unit = mod.foreachInfo(f)
}
-/** Wraps modules or statements with their respective described nodes.
- * Descriptions come from [[DescriptionAnnotation]]. Describing a
- * module or any of its ports will turn it into a [[DescribedMod]].
- * Describing a Statement will turn it into a [[DescribedStmt]]
+/** Wraps modules or statements with their respective described nodes. Descriptions come from [[DescriptionAnnotation]].
+ * Describing a module or any of its ports will turn it into a `DescribedMod`. Describing a Statement will turn it into
+ * a (private) `DescribedStmt`.
*
* @note should only be used by VerilogEmitter, described nodes will
* break other transforms.