diff options
Diffstat (limited to 'src/main/scala/firrtl/AddDescriptionNodes.scala')
| -rw-r--r-- | src/main/scala/firrtl/AddDescriptionNodes.scala | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/AddDescriptionNodes.scala b/src/main/scala/firrtl/AddDescriptionNodes.scala index 213bfad6..bd3412a4 100644 --- a/src/main/scala/firrtl/AddDescriptionNodes.scala +++ b/src/main/scala/firrtl/AddDescriptionNodes.scala @@ -68,11 +68,9 @@ private case class DescribedMod(description: Description, * @note should only be used by VerilogEmitter, described nodes will * break other transforms. */ -class AddDescriptionNodes extends Transform with PreservesAll[Transform] { - def inputForm = UnknownForm - def outputForm = UnknownForm +class AddDescriptionNodes extends Transform with DependencyAPIMigration with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[firrtl.transforms.BlackBoxSourceHelper], Dependency[firrtl.transforms.FixAddingNegativeLiterals], Dependency[firrtl.transforms.ReplaceTruncatingArithmetic], @@ -85,9 +83,9 @@ class AddDescriptionNodes extends Transform with PreservesAll[Transform] { Dependency[firrtl.transforms.VerilogRename], Dependency(firrtl.passes.VerilogPrep) ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty def onStmt(compMap: Map[String, Seq[String]])(stmt: Statement): Statement = { stmt.map(onStmt(compMap)) match { |